AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 SHUFPS Shuffle Packed Single-Precision Floating-Point Moves two of the four packed single-precision floating-point values in the first source operand to the low-order quadword of the destination (first source) and moves two of the four packed single-precision floating-point values in the second source operand to the high-order quadword of the destination. In each case, the value of the destination doubleword is determined by a two-bit field in the immediate-byte operand, as shown in Table 1-8 on page 355. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description SHUFPS xmm1, xmm2/mem128, imm8 0F C6 /r ib Shuffles packed single-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and puts the result in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 mux imm8 7 0 354 SHUFPS 127 96 95 64 63 32 31 0 mux shufps.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Table 1-8. Immediate-Byte Operand Encoding for SHUFPS Destination Bits Filled Related Instructions SHUFPD rFLAGS Affected None MXCSR Flags Affected None Immediate-Byte Bit Field 31–0 1–0 63–32 3–2 95–64 5–4 127–96 7–6 Value of Bit Field Source 1 Bits Moved Source 2 Bits Moved 0 31–0 — 1 63–32 — 2 95–64 — 3 127–96 — 0 31–0 — 1 63–32 — 2 95–64 — 3 127–96 — 0 — 31–0 1 — 63–32 2 — 95–64 3 — 127–96 0 — 31–0 1 — 63–32 2 — 95–64 3 — 127–96 SHUFPS 355
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