AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE Exceptions 128 MAXSD M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank. Exception Real Invalid opcode, #UD X X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception Exception, #XF while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions for details. SIMD Floating-Point Exceptions Invalid-operation exception (IE) X X X A source operand was an SNaN or QNaN value. Denormalized-operand exception (DE) X X X A source operand was a denormal value.
26568—Rev. 3.05—September 2003 AMD64 Technology MAXSS Maximum Scalar Single-Precision Floating- Point Compares the single-precision floating-point value in the low-order 32 bits of the first source operand with the single-precision floating-point value in the low-order 32 bits of the second source operand and writes the numerically greater of the two values in the low-order 32 bits of the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or a 32-bit memory location. The three high-order doublewords of the destination XMM register are not modified. Mnemonic Opcode Description MAXSS xmm1, xmm2/mem32 F3 0F 5F /r Compares scalar single-precision floating-point values in an XMM register and another XMM register or 32-bit memory location and writes the greater of the two values in the destination XMM register. If both source operands are equal to zero, the value in the second source operand is returned. If either operand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second source operand is written to the destination. Related Instructions MAXPD, MAXPS, MAXSD, MINPD, MINPS, MINSD, MINSS, PFMAX rFLAGS Affected None xmm1 xmm2/mem32 127 32 31 0 127 32 31 0 maximum maxss.eps MAXSS 129
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