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AMD64 Technology 26568—Rev. 3.05—September 2003 DIVSD Divide Scalar Double-Precision Floating-Point Divides the double-precision floating-point value in the low-order quadword of the first source operand by the double-precision floating-point value in the low-order quadword of the second source operand and writes the result in the low-order quadword of the destination (first source). The high-order quadword of the destination is not modified. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description DIVSD xmm1, xmm2/mem64 F2 0F 5E /r Divides low-order double-precision floating-point value in an XMM register by the low-order double-precision floating-point value in another XMM register or in a 64- or 128-bit memory location. Related Instructions DIVPD, DIVPS, DIVSS rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE 108 DIVSD xmm1 xmm2/mem64 127 64 63 0 127 64 63 0 divide M M M M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank. divsd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception Exception, #XF while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions Invalid-operation exception (IE) X X X A source operand was an SNaN value. X X X ±Zero was divided by ±zero. X X X ±infinity was divided by ±infinity. Overflow exception (OE) X X X A rounded result was too large to fit into the format of the destination operand. Underflow exception (UE) X X X A rounded result was too small to fit into the format of the destination operand. Denormalized-operand exception (DE) X X X A source operand was a denormal value. Zero-divide exception (ZE) X X X A non-zero number was divided by zero. Precision exception (PE) X X X A result could not be represented exactly in the destination format. DIVSD 109
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