AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 PSRLW Packed Shift Right Logical Words Right-shifts each of the packed 16-bit values in the first source operand by the number of bits specified in the second operand and writes each shifted value in the corresponding word of the destination (first source). The first source/destination and second source operands are: � an XMM register and another XMM register or 128-bit memory location, or � an XMM register and an immediate byte value. The high-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greater than 15, the destination is cleared to 0. Mnemonic Opcode Description PSRLW xmm1, xmm2/mem128 66 0F D1 /r Right-shifts packed words in an XMM register by the amount specified in the low 64 bits of an XMM register or 128-bit memory location. PSRLW xmm, imm8 66 0F 71 /2 ib Right-shifts packed words in an XMM register by the amount specified in an immediate byte value. 306 PSRLW
26568—Rev. 3.05—September 2003 AMD64 Technology Related Instructions PSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ rFLAGS Affected None MXCSR Flags Affected None shift right shift right . . . . . . . . . . . . . . . . xmm1 xmm2/mem128 . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 127 64 63 0 . . shift right xmm imm8 . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . shift right psrlw-128.eps PSRLW 307 7 0
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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