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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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<strong>AMD</strong><strong>64</strong> Technology 26568—Rev. 3.05—September 2003<br />

Exceptions<br />

Exception Real<br />

Invalid opcode, #UD X<br />

X<br />

314 PSUBQ<br />

Virtual<br />

8086 Protected Cause of Exception<br />

X<br />

X<br />

X<br />

X<br />

The SSE2 instructions are not supported, as indicated by bit<br />

26 of CPUID standard function 1.<br />

The emulate bit (EM) of CR0 was set to 1.<br />

X X X The operating-system FXSAVE/FXRSTOR support bit<br />

(OSFXSR) of CR4 is cleared to 0.<br />

Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1.<br />

Stack, #SS X X X A memory address exceeded the stack segment limit or was<br />

non-canonical.<br />

General protection, #GP X<br />

X<br />

X<br />

X<br />

A memory address exceeded a data segment limit or was<br />

non-canonical.<br />

A null data segment was used to reference memory.<br />

X X X The memory operand was not aligned on a 16-byte<br />

boundary.<br />

Page fault, #PF X X A page fault resulted from the execution of the instruction.

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