AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exceptions Exception Real Invalid opcode, #UD X Device not available, #NM X X Virtual 8086 Protected Cause of Exception 264 PMOVMSKB X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1.
26568—Rev. 3.05—September 2003 AMD64 Technology PMULHUW Packed Multiply High Unsigned Word Multiplies each packed unsigned 16-bit values in the first source operand by the corresponding packed unsigned word in the second source operand and writes the high-order 16 bits of each intermediate 32-bit result in the corresponding word of the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PMULHUW xmm1, xmm2/mem128 66 0F E4 /r Multiplies packed 16-bit values in an XMM register by the packed 16-bit values in another XMM register or 128-bit memory location and writes the high-order 16 bits of each result in the destination XMM register. Related Instructions PMADDWD, PMULHW, PMULLW, PMULUDQ rFLAGS Affected None MXCSR Flags Affected None multiply xmm1 xmm2/mem128 . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . multiply 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . pmulhuw-128.eps PMULHUW 265
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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