AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Table 1-6. Immediate-Byte Operand Encoding for PSHUFLW Related Instructions PSHUFD, PSHUFHW, PSHUFW rFLAGS Affected None MXCSR Flags Affected None Destination Bits Filled Immediate-Byte Bit Field 15–0 1–0 31–16 3–2 47–32 5–4 63–48 7–6 284 PSHUFLW Value of Bit Field Source Bits Moved 0 15–0 1 31–16 2 47–32 3 63–48 0 15–0 1 31–16 2 47–32 3 63–48 0 15–0 1 31–16 2 47–32 3 63–48 0 15–0 1 31–16 2 47–32 3 63–48
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PSHUFLW 285
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