AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVDQU Move Unaligned Double Quadword Moves an unaligned 128-bit (double quadword) value: � from an XMM register or 128-bit memory location to another XMM register, or � from an XMM register to another XMM register or 128-bit memory location. Mnemonic Opcode Description MOVDQU xmm1, xmm2/mem128 F3 0F 6F /r Moves 128-bit value from an XMM register or unaligned 128-bit memory location to the destination XMM register. MOVDQU xmm1/mem128, xmm2 F3 0F 7F /r Moves 128-bit value from an XMM register to the destination XMM register or unaligned 128-bit memory location. Memory operands that are not aligned on a 16-byte boundary do not cause a generalprotection exception. Related Instructions MOVD, MOVDQA, MOVDQ2Q, MOVQ, MOVQ2DQ rFLAGS Affected None xmm1 xmm2/mem128 127 0 152 MOVDQU 127 0 copy xmm1/mem128 xmm2 127 0 127 0 copy movdqu.eps
26568—Rev. 3.05—September 2003 AMD64 Technology MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indcated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned-memory reference was performed while alignment checking was enabled. MOVDQU 153
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