AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exception Real General protection, #GP X X X 38 COMISD Virtual 8086 Protected Cause of Exception A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception Exception, #XF while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions Invalid-operation exception (IE) X X X A source operand was an SNaN or QNaN value. Denormalized-operand exception (DE) X X X A source operand was a denormal value.
26568—Rev. 3.05—September 2003 AMD64 Technology COMISS Compare Ordered Scalar Single-Precision Floating-Point Performs an ordered comparison of the single-precision floating-point value in the low-order 32 bits of an XMM register with the single-precision floating-point value in the low-order 32 bits of another XMM register or a 32-bit memory location and sets the ZF, PF, and CF bits in the rFLAGS register to reflect the result of the comparison. The result is unordered if one or both of the operand values is a NaN. The OF, AF, and SF bits in rFLAGS are set to zero. If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated. Mnemonic Opcode Description COMISS xmm1, xmm2/mem32 0F 2F /r Compares single-precision floating-point values in an XMM register and an XMM register or 32-bit memory location. Sets rFLAGS. xmm1 xmm2/mem32 127 31 0 127 31 0 63 0 31 compare rFLAGS Result of Compare ZF PF CF Unordered 1 1 1 Greater Than 0 0 0 Less Than 0 0 1 Equal 1 0 0 0 comiss.eps COMISS 39
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