AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exceptions Exception Real Invalid opcode, #UD X 262 PMINUB Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. X X X Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X A memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction.
26568—Rev. 3.05—September 2003 AMD64 Technology PMOVMSKB Packed Move Mask Byte Moves the most-significant bit of each byte in the source operand to the destination, with zero-extension to 32 bits. The destination and source operands are a 32-bit general-purpose register and an XMM register. The result is written to the low-order word of the general-purpose register. Mnemonic Opcode Description PMOVMSKB reg32, xmm 66 0F D7 /r Moves most-significant bit of each byte in an XMM register to loworder word of a 32-bit general-purpose register. Related Instructions MOVMSKPD, MOVMSKPS rFLAGS Affected None MXCSR Flags Affected None 32 0 reg32 xmm 15 . . ... . . . . ... . . ... . . . . ... 0 127 119 111 103 95 87 79 71 63 55 47 39 31 23 15 7 0 . . . . . . . . . copy . . . . . copy pmovmskb-128.eps PMOVMSKB 263
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