AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exceptions Exception Real Invalid opcode, #UD X X 182 MOVSD Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled.
26568—Rev. 3.05—September 2003 AMD64 Technology MOVSS Move Scalar Single-Precision Floating-Point Moves a scalar single-precision floating-point value: � from the low-order 32 bits of an XMM register or a 32-bit memory location to the low-order 32 bits of another XMM register, or � from a 32-bit memory location to the low-order 32 bits of an XMM register, with zero-extension to 128 bits. If the source operand is an XMM register, the high-order 96 bits of the destination XMM register are not modified. If the source operand is a memory location, the highorder 96 bits of the destination XMM register are cleared to all 0s. Mnemonic Opcode Description MOVSS xmm1, xmm2/mem32 F3 0F 10 /r Moves single-precision floating-point value from an XMM register or 32-bit memory location to an XMM register. MOVSS xmm1/mem32, xmm2 F3 0F 11 /r Moves single-precision floating-point value from an XMM register to an XMM register or 32-bit memory location. MOVSS 183
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