AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVHPD Move High Packed Double-Precision Floating-Point Moves a double-precision floating-point value: � from a 64-bit memory location to the high-order 64 bits of an XMM register, or � from the high-order 64 bits of an XMM register to a 64-bit memory location. The low-order 64 bits of the destination XMM register are not modified. Mnemonic Opcode Description MOVHPD xmm, mem64 66 0F 16 /r Moves double-precision floating-point value from a 64-bit memory location to an XMM register. MOVHPD mem64, xmm 66 0F 17 /r Moves double-precision floating-point value from an XMM register to a 64-bit memory location. Related Instructions MOVAPD, MOVLPD, MOVMSKPD, MOVSD, MOVUPD rFLAGS Affected None xmm mem64 127 64 63 0 mem64 63 0 156 MOVHPD xmm 63 0 copy 127 32 31 0 copy movhpd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. MOVHPD 157
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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