AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVNTDQ Move Non-Temporal Double Quadword Stores a 128-bit (double quadword) XMM register value into a 128-bit memory location. This instruction indicates to the processor that the data is non-temporal, and is unlikely to be used again soon. The processor treats the store as a write-combining (WC) memory write, which minimizes cache pollution. The exact method by which cache pollution is minimized depends on the hardware implementation of the instruction. For further information, see “Memory Optimization” in Volume 1. MOVNTDQ is weakly-ordered with respect to other instructions that operate on memory. Software should use an SFENCE instruction to force strong memory ordering of MOVNTDQ with respect to other stores. Mnemonic Opcode Description MOVNTDQ mem128, xmm 66 0F E7 /r Stores a 128-bit XMM register value into a 128-bit memory location, minimizing cache pollution. Related Instructions MOVNTI, MOVNTPD, MOVNTPS, MOVNTQ rFLAGS Affected None MXCSR Flags Affected None mem128 xmm 127 0 170 MOVNTDQ 127 0 copy movntdq.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (CR0.EM) was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (CR4.OSFXSR) was cleared to 0. Device not available, #NM X X X The task-switch bit (CR0.TS) was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. The destination operand was in a non-writable segment. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from executing the instruction. MOVNTDQ 171
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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