AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 PADDB Packed Add Bytes Adds each packed 8-bit integer value in the first source operand to the corresponding packed 8-bit integer in the second source operand and writes the integer result of each addition in the corresponding byte of the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PADDB xmm1, xmm2/mem128 66 0F FC /r Adds packed byte integer values in an XMM register and another XMM register or 128-bit memory location and writes the result in the destination XMM register. This instruction operates on both signed and unsigned integers. If the result overflows, the carry is ignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 8 bits of each result are written in the destination. Related Instructions PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW rFLAGS Affected None MXCSR Flags Affected None 127 0 127 0 add xmm1 xmm2/mem128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 PADDB add . . . . . . . . . . . . . . paddb-128.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PADDB 213
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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