AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

AMD64 Technology 26568—Rev. 3.05—September 2003
MASKMOVDQU Masked Move Double Quadword Unaligned
Stores bytes from the first source operand as selected by the sign bits in the second
source operand (sign-bit is 0 = no write and sign-bit is 1 = write) to a memory location
specified in the DS:rDI registers. The first source operand is an XMM register, and the
second source operand is another XMM register. The store address may be unaligned.
Mnemonic Opcode Description
MASKMOVDQU xmm1, xmm2 66 0F F7 /r Store bytes from an XMM register selected by a mask value in
another XMM register to DS:rDI.
xmm1
127 0
. . . . . . .
select
. . . . . . .
Memory
. . . . . . .
select
. . . . . . .
A mask value of all 0s results in the following behavior:
� No data is written to memory.
� Code and data breakpoints are not guaranteed to be signaled in all implementations.
� Exceptions associated with memory addressing and page faults are not guaranteed
to be signaled in all implementations.
� The protection features of memory regions mapped as UC or WP are not guaranteed
to be enforced in all implementations.
120 MASKMOVDQU
xmm2/mem128
127 0
. . . . . . .
store address
. . . . . . .
DS:rDI
maskmovdqu.eps