AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

26568—Rev. 3.05—September 2003 AMD64 Technology
MXCSR Flags Affected
FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE
Exceptions
M M
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note:
A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.
Exception Real
Invalid opcode, #UD X
X
X
Virtual
8086 Protected Cause of Exception
X
X
X
X
X
X
The SSE2 instructions are not supported, as indicated by bit
26 of CPUID standard function 1.
The emulate bit (EM) of CR0 was set to 1.
The operating-system FXSAVE/FXRSTOR support bit
(OSFXSR) of CR4 was cleared to 0.
X X X There was an unmasked SIMD floating-point exception
while CR4.OSXMMEXCPT = 0.
See SIMD Floating-Point Exceptions, below, for details.
Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1.
Stack, #SS X X X A memory address exceeded the stack segment limit or was
non-canonical.
General protection, #GP X
X
X
X
A memory address exceeded a data segment limit or was
non-canonical.
A null data segment was used to reference memory.
X X X The memory operand was not aligned on a 16-byte
boundary.
Page fault, #PF X X A page fault resulted from the execution of the instruction.
SIMD Floating-Point
Exception, #XF
X X X There was an unmasked SIMD floating-point exception
while CR4.OSXMMEXCPT = 1.
See SIMD Floating-Point Exceptions, below, for details.
CVTPD2DQ 47