AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 PINSRW Packed Insert Word Inserts a 16-bit value from the low-order word of a 32-bit general purpose register or a 16-bit memory location into an XMM register. The location in the destination register is selected by the immediate byte operand, as shown in Table 1-3 on page 251. The other words in the destination register operand are not modified. Mnemonic Opcode Description PINSRW xmm, reg32/mem16, imm8 66 0F C4 /r ib Inserts a 16-bit value from a general-purpose register or memory location into an XMM register. xmm 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 32 imm8 7 0 select word position for insert 250 PINSRW reg32/mem16 15 0 pinsrw-128.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Table 1-3. Immediate-Byte Operand Encoding for 128-Bit PINSRW Related Instructions PEXTRW rFLAGS Affected None MXCSR Flags Affected None Exceptions Immediate-Byte Bit Field 2–0 Exception Real Invalid opcode, #UD X Value of Bit Field Destination Bits Filled 0 15–0 1 31–16 2 47–32 3 63–48 4 79–64 5 95–80 6 111–96 7 127–112 Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. X X X Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. PINSRW 251
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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