AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Table 1-7. Immediate-Byte Operand Encoding for SHUFPD Destination Bits Filled Related Instructions SHUFPS rFLAGS Affected None MXCSR Flags Affected None Exceptions Immediate-Byte Bit Field 63–0 0 127–64 1 Exception Real Invalid opcode, #UD X X Value of Bit Field 352 SHUFPD Source 1 Bits Moved Source 2 Bits Moved 0 63–0 — 1 127–64 — 0 — 63–0 1 — 127–64 Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1.
26568—Rev. 3.05—September 2003 AMD64 Technology Exception Real Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X Virtual 8086 Protected Cause of Exception X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. SHUFPD 353
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