AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVUPD Move Unaligned Packed Double-Precision Floating-Point Moves two packed double-precision floating-point values: � from an XMM register or 128-bit memory location to another XMM register, or � from an XMM register to another XMM register or 128-bit memory location. Mnemonic Opcode Description MOVUPD xmm1, xmm2/mem128 66 0F 10 /r Moves two packed double-precision floating-point values from an XMM register or unaligned 128-bit memory location to an XMM register. MOVUPD xmm1/mem128, xmm2 66 0F 11 /r Moves two packed double-precision floating-point values from an XMM register to an XMM register or unaligned 128bit memory location. xmm1 xmm2/mem28 127 64 63 0 Memory operands that are not aligned on a 16-byte boundary do not cause a generalprotection exception. 186 MOVUPD 127 64 63 0 copy xmm1/mem28 xmm2 127 64 63 0 127 64 63 copy copy copy movupd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Related Instructions MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSD rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned-memory reference was performed while alignment checking was enabled. MOVUPD 187
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