AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X 328 PUNPCKHDQ Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction.
26568—Rev. 3.05—September 2003 AMD64 Technology PUNPCKHQDQ Unpack and Interleave High Quadwords Unpacks the high-order quadwords from the first and second source operands and packs them into interleaved quadwords in the destination (first source). The first source/destination is an XMM register, and the second source operand is another XMM register or 128-bit memory location. The low-order quadwords of the source operands are ignored. If the second source operand is all 0s, the destination contains the quadword from the first source operand zero-extended to 128 bits. This operation is useful for expanding unsigned 64-bit values to unsigned 128-bit operands for subsequent processing that requires higher precision. Mnemonic Opcode Description PUNPCKHQDQ xmm1, xmm2/mem128 66 0F 6D /r Unpacks high-order quadwords in an XMM register and another XMM register or 128-bit memory location and packs them into interleaved quadwords in the destination XMM register. Related Instructions xmm1 xmm2/mem128 127 64 63 0 copy copy 127 127 64 63 0 64 63 0 punpckhqdq.eps PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLQDQ, PUNPCKLWD PUNPCKHQDQ 329
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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