Xilinx Reliability Monitor Report - Quarter 4 CY 2001

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Jan. 1, 2002 P. 216 Board Level Reliability Test FG676, FG680, FG860, & FG1156 ®
Package Details Motherboard Design & Assembly Details – 4 Layer, FR-4, 1.6mm Thick, OSP Finish – 0.38mm Pad Diameter/0.53mm Solder Mask Opening (NSMD Pads) – 0.20mm SS Laser Cut Stencil, 0.43mm Aperture Opening, No Clean Paste Test Conditions – TC1 : -40125 o C, 15 minutes ramps,15 minutes dwells, 1 cycle/hour – TC2 : -55125 o C, 3 minutes ramps,12 minutes dwells, 2 cycles/hour – TC3 : 0 100 o C, 10 minutes ramps, 5 minutes dwells, 2 cycles/hour Failure Criteria – Continuous Scanning of Daisy Chain Nets (Every 2 minutes) – Threshold Resistance: 500 ohms – OPEN: An Event with Resistance of Net > Threshold Resistance – FAIL: At Least 2 OPENs within a Temperature Cycle – Log 15 FAILURES for each Net Jan. 1, 2002 P. 217 Package Size I/O Pitch Ball Size Pad Opening Pad Type Die Size Substrate FG860 (SBGA) 42.5x42.5 860 1.0 0.6 0.48 SMD 22.45x21.44x0.3 0.98 Thk, 3 Layer FG1156 (PBGA) 35x35 1156 1.0 0.6 0.48 SMD 23.11x21.13x0.3 0.56 Thk, 4 Layer FG676 (PBGA) 27x27 676 1.0 0.6 0.48 SMD 17.8x17.8x0.3 0.56 Thk, 4 Layer FG680 (SBGA) 40x40 680 1.0 0.6 0.48 SMD 20.3x20.3x0.3 0.98 Thk, 3 Layer All Dimensions in mm 2nd Level Reliability Test Xilinx FG676, FG680, FG860, &FG1156 ®
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Jan. 1, 2002 P. 1 The Reliability D
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Jan. 1, 2002 P. 3 TABLE OF CONTENTS
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Jan. 1, 2002 P. 5 2.1 Wafer Process
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Jan. 1, 2002 P. 7 2.3 Device Qualif
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Jan. 1, 2002 4. Failure Analysis: A
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Jan. 1, 2002 P. 11 F/A ACRONYM DESC
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Temperature (C o ) XILINX Typical C
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Jan. 1, 2002 P. 15 ESD and Latch-up
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(1) Measured on XC1765D (2) Measure
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Jan. 1, 2002 P.19 Failure Rate Summ
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Combined Lots: Failures: Device on
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Jan. 1, 2002 Combined Started Lot:
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Xilinx Reliability Monitor Report - Quarter 4 CY 2001

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