PowerFlex 750-Series AC Drives User Manual

Programming and Parameters 3-71FileGroupNameNo. Description635 Spd Options CtrlSpeed Options ControlValuesRead-WriteData TypeOptionsReservedReservedReservedReservedReservedReservedReservedDelayed RefAuto Tach SWJog No IntegSpdErrFilterSpdRegIntHldSpdRegIntResStpNoSCrvAccRamp DisableRamp HoldDefault 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 = False1 = TrueSPEED CONTROLSpeed RegulatorConfigures options related to Speed Control as follows:Bit 0 “Ramp Hold” – The output of the speed reference ramp will stop changing and hold its output constant while this bit is set. When this bit is clear,the ramp output will be allowed to change. If this bit becomes set while P594 [Ramped Spd Ref] is in the S Curve region, the S Curve will be allowedto complete before the output is held.Bit 1 “Ramp Disable” – When set, the speed reference ramp will become disabled. P594 [Ramped Spd Ref] will track the ramp input.Bit 2 “StpNoSCrvAcc” – There are some conditions where the drive may continue to accelerate briefly following a request to stop. This will occur if thedrive was in the process of accelerating on an S Curve when the stop request occurred. This bit enables an option to discontinue accelerationimmediately when the stop request occurs. The S Curve profile that was in process will then change to a linear decel ramp.Bit 3 “SpdRegIntRes” – When set, the P654 [Spd Reg Int Out] which is the output of the Vector mode speed regulator’s integral term will be forced tozero. The same result can be achieved by setting the regulator’s integral gain to zero.Bit 4 “SpdRegIntHld” – When set, the P654 [Spd Reg Int Out] which is the output of the Vector mode speed regulator’s integral term will stopchanging and be held constant. Other conditions in the drive such as a limit condition in P945 [At Limit Status] may have the same result.Bit 5 “SpdErrFilter” – When set, the speed error filter in the drive’s Vector mode speed regulator will be configured for a single stage low pass filter.When clear, the error filter will be configured for a two stage low pass filter. The two stage configuration is the normal or default setting for the errorfilter.Bit 6 “Jog No Integ” – When set, the P654 [Spd Reg Int Out] which is the output of the Vector mode speed regulator’s integral term will be forced tozero while jogging.Bit 7 “Auto Tach SW” – This bit is used to enable the Automatic Tach Switchover feature. This feature is used to switch motor velocity feedbacksources from the Primary to Alternate source in the event that the primary source fails. This switchover can take place while the drive is running. TheP936 [Drive Status 2] Bit 5 “FdbkLoss SwO” will indicate clear when the Primary source is active and set when the alternate source is active. Clearingthe (Auto Tach SW) bit when the alternate source is active will restore control to the Primary source, provided that the primary source is functioning.If the (Auto Tach SW) bit remains off, then the Automatic Tach Switchover feature will be disabled.Bit 8 “Delayed Ref” – When this bit is set, an additional processor scan delay period is inserted between the P594 [Ramped Spd Ref] and the input tothe Speed Reference filter. This delay is intended to be used in applications where multiple, coordinated drives are used. A drive that supplies thespeed reference for use by other drives to follow would typically use this delay. The delay would allow time for the speed reference to reach the otherunits before it is acted upon by the sourcing unit, thereby synchronizing the speed reference among all units. When this bit is clear, no speedreference delay is inserted.PowerFlex 750-Series User Manual – Publication 750-UM001C-EN-P – September 2009