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support 10 Mb / s. But ENC28J60 only supports SPI
mode 00, ie CPOL = 0 and CPHA = 0. In addition, SPI
port requirements for the idle state SCK is low and does
not support the clock polarity selection.
2. TCP / IP protocol stack to streamline and achieved:
taking into account the MCU RAM storage space
constraints and specific application requirements,
reasonable to simplify TCP / IP protocol stack, select the
realization of ARP, IP, ICMP, TCP, and HTTP protocols.
3.Physical layer implementation of the interface: the
physical layer interface for the ENC28J60 the driver, the
hardware is a circuit ENC28J60 the physical cable link,
medium access control, frame transmit and receive
functions, but shall be driven with the upper protocol
interface procedures, to achieve to send and receive data
frames.
4. The network layer protocol implementation:
network-layer protocols, including ARP, IP, ICMP
protocols.
Know both the network connection between the
physical address, while the ARP protocol is address
resolution protocol to achieve IP address to physical
address conversion. Internet Protocol (IP) is responsible
for the message sent from one host to another host. ICMP
protocol is Internet Control Message Protocol for IP hosts,
passing control messages between routers. Control of
news is that the network is clear, host is up, routing is
available and so the network itself the message.
B. Ethernet Buffer
Ethernet buffer contains the Ethernet controller for use
to send and receive memory, the buffer size is 8KB, is
divided into separate receive and send buffer space. Host
controller using the SPI interface can send and receive
capacity and location of storage of their programming.
Receive buffer consists of a hardware management cycle
FIFO buffer composition. Register for ERXSTH:
ERXSTL and ERXNDH: ERXNDL as a pointer, the
definition of buffer capacity and its memory location.
When you accept the logic is disabled, the main
controller can be programmed ERXST and ERXND
pointers. When the receiver logic is used, not allowed to
modify the pointer. 8KB memory has not been set up to
receive FIFO buffer space, can be used as send buffer.
Main controller is responsible for managing the data
packets sent within the storage buffer. When the master
controller decided to send a packet, ERXST and ERXND
the pointer will be programmed to point to send data
packets to be sent within a buffer address. Hardware does
not check whether the start and end addresses overlap
with the receive buffer. Main controller through separate
read and write pointers (ERDPT and EWRPT) as well as
read, write buffer SPI commands to access the contents of
the Ethernet buffer.
Receive buffer free space calculation method:
If ERXWRPT>ERXRDPT, then
Freespace=(ERXND-ERXST)-(ERXWRPT-ERXRDPT)
If ERXWRPT=ERXRDPT, then
Freespace=(ERXND-ERXST)
Else
Freespace=ERXRDPT-ERXWRPT-1
When the order reads receive buffer when the receive
buffer memory in the read data will be folded back to the
bottom of the first part to continue reading. In calculating
the checksum, the integrated DMA controller to read
buffer; when the copy storage space, you must read and
write buffer. DMA follow the rules of SPI access to the
same turn back. The remote PC, transfer data packets
over the Internet for twisted-pair physical medium to
reach the local embedded systems, first of all through the
isolation transformer coupled into the Ethernet control
chip ENC28J60 in, ENC28J60 embedded in the physical
layer and MAC layer to perform the address resolution
protocol, and then to the LPC2132 microcontroller,
LPC2132 implementation of the streamlining of TCP / IP
protocol stack, remove the TCP / IP header, get useful
data, and then embedded devices to achieve remote
control and monitoring of the Internet.
C. Duplex Mode Configuration
ENC28J60 does not support duplex mode adaptive
(auto-negotitation). If ENC28J60 enable duplex mode to
connect to the Ethernet controller adaptive, then it will be
detected as a half-duplex devices. This set is a full-duplex
mode communications. When MACON3.FULDPX = 1
and PHCON.1PDPXMD = 1 Shi, ENC28J60 work in
full-duplex mode. If these two bits, only one bit is cleared,
then the ENC28J60 the working state of uncertainty and
can not work properly. Master in the mode switching
device does not send any data packets to maintain
ECON1.TXRTS cleared. In full-duplex mode, you can
also receive and send data packets. In this case, when
sending data packets will not occur any conflict. In fullduplex
mode (MACON3.FULDPX = 1), the hardware
flow control is controlled by sending pause frames to
achieve. Pause control frame is 64 bytes long, from the
reserved multicast destination address 01-80-C2-00-00-
01, sending node, the source address, a special suspension
of operation code, two bytes of the suspension timer
value, and fill / CRC bits.
D. In the river sediment measurement
With the modernization of China's development of
hydrology and water resources information collection,
transmission, processing and prediction of intelligence
have been gradually speed up the construction progress of
the hydrological work flow measurement, measuring sand,
measuring rainfall is heavy throughout the hydrological
work in the weight, the accuracy of these monitoring data
for China's flood control and drought and water
management conservation significance. The use of the
existing hydrological stations in river hydrology
cableway will we have designed an underwater camera
equipment sunk a pre-set vertical position, when the bank
issued the workstation computer, camera control
commands, the underwater camera to camera began to
water samples, and the image transmitted to the image
acquisition card, and then will be collected by the ARM
image data transmission to the bank workstations.
Riparian workstation computer for various pieces of
image denoising, segmentation, calculation and
processing, and thus arrive at the river sediment content.
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