SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA94 FunctionalityThis is achieved by grouping the modules into a single port on the SuperHyway, andhandling any data size, data rate and endianness issues transparently. This ensuresthat future and existing modules can maintain both architectural and designcompatibility with existing SuperH, ST and Hitachi design libraries 1 whilstproviding a simple integration strategy for SH-5 systems in the future.5.2 Functionality5.2.1 OverviewThe system views the majority of the SH-5 peripherals as a single SuperHywaymodule. The bridge maps these onto a single contiguous 32 Mbyte area of memory.The peripheral bridge allocates a segment of this memory space to each device, andensures that the view of the peripheral visible to the system is consistent. Thisincludes responsibility for ensuring that all modules have the same representationof address and data for their registers, and that features such as unmapped areas ofmemory, and/or addition functionality is handled consistently.For the Eval implementation, the peripheral subsystem divides it’s memory spaceinto a number of contiguous slots as below:Slot 0 is reserved for the bridge statusSlots S1 to S15 are reserved for SuperHyway type 2 peripheralsSlots P0 to P15 and PEX are reserved for PP-Bus peripheralsThe peripheral subsystem also maintains the state associated with the peripheralsubsystem as a whole, handles the protocol and format changes required to mapSuperHyway operations onto those required by the peripheral bus, and maintainsthe status associated with erroneous accesses to these devices.D R A FT1. SH7750, SH-4 CORE, XX-ST20, ST40SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0