SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 121Interrupt control register clear(ICR.CLEAR)INTCBASE + 0x08Field Bits Size Volatile? Synopsis Type— [31:16] 16 — RESERVED RESOperationPriority registers 0 to 7 (INTPRI n)RESERVEDWhen read Returns 0When writtenHARD reset 0IgnoredThese eight registers control the priority associated with each interrupt source.These are 32-bit registers with 4 bits per priority. Register 0 is used to specify thepriorities of interrupt numbers 0 through 7, register 1 for interrupt numbers 8through 15 and so on. The format of these registers is shown in Table 45.Interrupt priority register n (INTPRI n)n={0..7}Table 44: Interrupt control register clearINTCBASE + 0x10 +8*nField Bits Size Volatile? Synopsis TypeINTERRUPT 8n [3:0] 4 — Priority of interrupt 8n RWINTERRUPT8n + 1INTERRUPT8n + 2OperationWhen readWhen writtenContains the priority of the interruptReturns current valueUpdates current valueD R A FTHARD reset 0[7:4] 4 — Priority of interrupt 8n + 1 RWAs for interrupt 8n[11:8] 4 — Priority of interrupt 8n + 2 RWAs for interrupt 8nTable 45: Interrupt priority register n (INTPRIn) a05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System