SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAInterrupt exception handling and priority 117Interrupt causes(in order of defaultprecedence) aInterruptnumberINTEVT codeInterrupt priorityResetvalueTMU TUNI0 32 0x400 0 ProgrammableTUNI1 33 0x420 0TUNI2 34 0x440 0TICPI2 35 0x460RTC ATI 36 0x480 0PRI 37 0x4A0CUI 38 0x4C0SCIF ERI 39 0x700 0RXI 40 0x720BRI 41 0x740TXI 42 0x760Reserved 43 0x1C0 044 0x1E045 to 62 0xC00 to 0xE20WDT ITI 63 0x560 0Table 42: Interrupt causes and prioritiesa. TUNI0 to TUNI2: Underflow interrupts, see TMU section.TICPI2: Input capture interrupt, see TMU sectionATI: Alarm interrupt, see RTC sectionPRI: Periodic interrupt, see RTC sectionCUI: Carry-up interrupt, see RTC sectionERI: Receive error interrupt, see SCIF sectionRXI: Receive-data-full interrupt, see SCIF sectionTXI: Transmit-data-empty interrupt, see SCIF section.DMTE0 to DMTE3: DMAC transfer end interruptsDAERR: DMAC address error interruptITI: Interval timer interruptD R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System