SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA246 OperationInitializationClear TE and RE bitsin SCSCR2 to 0Set TFRST and RFRST bitsin SCFCR2 to 1Set CKE1 bit in SCSCR2(leaving TE and RE bitscleared to 0)Set data transfer formatin SCSMR2Set value in SCBRR21-bit interval elapsed?YesSet RTRG1–0, TTRG1–0,and MCE bits in SCFCR2Clear TFRST and RFRST bits to 0Set TE and RE bitsin SCSCR2 to 1,and set RIE, TIE, and REIE bitsEndWaitNo1. Set the clock selection in SCSCR2.Be sure to clear bits RIE and TIE,and bits TE and RE, to 0.2. Set the data transfer format inSCSMR2.3. Write a value corresponding to thebit rate into SCBRR2. (Notnecessary if an external clock isused.)4. Wait at least one bit interval, thenset the TE bit or RE bit in SCSCR2to 1. Also set the RIE, REIE, andTIE bits.D R A FTFigure 31: Sample SCIF initialization flowchartSetting the TE and RE bits enablesthe TxD2 and RxD2 pins to beused. When transmitting, the SCIFwill go to the mark state; whenreceiving, it will go to the idle state,waiting for a start bit.SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0