SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATASystemorganization2.1 IntroductionD R A FT2The SH-5 system architecture is modular. An SH-5 implementation consists of anumber of modules which communicate using one or more interconnects. Theinterconnect to which the CPU core is connected provides the main path to externalmemory. This interconnect provides a memory-mapped packet routing mechanismbetween modules. It is known as the SuperHyway and forms the backplane of highlyintegrated systems which use the SH-5. The SuperHyway specifies a protocol whichdefines how packets are represented and propagated. The name SuperHyway isgiven to the family of implementations of this protocol on SH-5 chips.A typical SH-5 implementation is a single chip which contains one or more CPUcores, one or more product-specific SH-5 modules, an interconnect, a peripheralsubsystem, an external memory interface and a module dedicated to supportingdebug of the core and system.2.2 SuperHyway architectureThe SuperHyway architecture provides the ‘glue’ that binds together a set of SH-5modules. A connection between the SuperHyway and an SH-5 module is called aport (sometimes referred to as a p-port). A SuperHyway port supports abi-directional flow of packets between the interconnect and an SH-5 module.The distinction between the SuperHyway architecture and implementation isimportant. This section, SuperHyway architecture, defines the abstractions that areused to build implementations containing a SuperHyway interconnect. Thearchitecture includes an abstract view of the packets, the SuperHyway, the port, aSH-5 module and the protocol.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System