SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA120 Register descriptionsInterrupt control register set(ICR.SET)INTCBASE + 0x00Field Bits Size Volatile? Synopsis Type— [31:16] 16 — RESERVED RESOperationRESERVEDWhen read Returns 0When writtenHARD reset 0IgnoredInterrupt control register clear(ICR.CLEAR)INTCBASE + 0x08Field Bits Size Volatile? Synopsis TypeIRLM 0 1 No IRL pin mode RWOperationWhen readWhen writtenHARD reset 00: IRL pins are used for level-encoded interrupt requests1: IRL pins are used as four independent interrupt requestsReturns current valueWrite 1 clears the bit to 0. Write 0 is ignored.— [15:1] 15 — ICR15 to ICR1 RWOperationWhen readWhen writtenTable 43: Interrupt control register setINTC provides those bits as output signals. External gluelogic can use those bits to implement additional feature infuture chip integration.D R A FTReturns current valueWrite 1 clears the bit to 0. Write 0 is ignored.HARD reset 0Table 44: Interrupt control register clearSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0