SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA126 Register descriptionsInterrupt disable register 0 and 1 (INTDSB0 and INTDSB1)This pair of 32-bit registers are used to examine and set bits in the 64-bit interruptmask. For each bit where the mask is set the corresponding interrupt is disabled.When either register is read, it will return the value of the mask, When written,each data bit which is ‘1’ will set the corresponding bit in the mask; each data bitswhich is ‘0’ is ignored. The format of these registers is shown in Table 48 andTable 49.Interrupt disable register 0 (INTDSB0)INTCBASE + 0x80Field Bits Size Volatile? Synopsis TypeINTERRUPT 0 0 1 — Interrupt 0 disable RWOperation aWhen readWhen writtenHARD reset 0Disables interrupt 0 to be passed to CPUReturns current value1: Sets bit 0 of mask0: IgnoredINTERRUPT 1 1 1 — Interrupt 1 disable RWOperation bWhen readWhen writtenHARD reset 0Disables interrupt 1 to be passed to CPUReturns current value1: Sets bit 1 of mask0: IgnoredINTERRUPT 2 2 1 — Interrupt 2 disable RWOperation bWhen readWhen writtenDisables interrupt 2 to be passed to CPUD R A FTReturns current value1: Sets bit 2 of mask0: Ignored...HARD reset 0Table 48: Interrupt disable register 0 (INTDSB0)SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0