SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA164 Register descriptionsRTC.RCR20x3CField Bits Size Volatile? Synopsis TypeADJ 2 1 ✓ Second adjustment RWOperationWhen readWhen writtenHARD reset 0Used for 30-second adjustment. When 1 is written to this bit,a value up to 29 seconds is rounded down to 00 seconds,and a value of 30 seconds or more is rounded up to 1 minute.The frequency divider circuits (RTC prescaler andRTC.R64CNT) are also reset at this time. This bit alwaysreturns 0 if readReturns current value0: Normal clock operation (Initial value)1: 30-second adjustment performedRTCEN 3 1 ✓ Oscillator enable RWOperationWhen readWhen writtenHARD reset 1Controls the operation of the RTC’s crystal oscillatorReturns current value0: NRTC crystal oscillator is halted1: RTC crystal oscillator is operated (Initial value)Table 71: RTC.RCR2D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 165RTC.RCR20x3CField Bits Size Volatile? Synopsis TypePESnwhere n is2, 1, 0[6:4] 3 ✓ Periodic interrupt enable RWOperationWhen readWhen writtenHARD reset 0These bits specify the period for periodic interruptsReturns current value000: No periodic interrupt generation (Initial value)001: Periodic interrupt generated at 1/256 second intervals010: Periodic interrupt generated at 1/64 second intervals011: Periodic interrupt generated at 1/16 second intervals100: Periodic interrupt generated at 1/4 second intervals101: Periodic interrupt generated at 1/2 second intervals110: Periodic interrupt generated at 1 second intervals111: Periodic interrupt generated at 2 second intervalsPEF 7 1 ✓ Periodic interrupt flag RWOperationWhen readWhen writtenHARD resetIndicates interrupt generation at the interval specified by bitsPES2–PES0. When this flag is set to 1, a periodic interrupt isgeneratedReturns current value0: Interrupt is not generated at interval specified by bits PES2to PES01: Interrupt is generated at interval specified by bits PES2 toPES0D R A FTUndefinedTable 71: RTC.RCR2a. The counter RTC.R64CNT continues to operate unless stopped by means of theRTCEN bit.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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