SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 183TMU.TCR[2]0x28Field Bits Size Volatile? Synopsis TypeCKEG [4:3] 2 - Clock edge RWOperationWhen readWhen writtenHARD reset 00Select the external clock input edge when an external clock isselected or the input capture function is usedReturns current value00: Count/input capture register set on rising edge01: Count/input capture register set on falling edge1X: Count/input capture register set on both rising and fallingedgesUNIE [5] 1 - Underflow interrupt control RWOperationWhen readWhen writtenHARD reset 0Controls enabling or disabling of interrupt generation whenthe UNF status flag is set to 1, indicating TCNT underflowReturns current value0: Interrupt due to underflow (TUNI) is not enabled1: Interrupt due to underflow (TUNI) is enableTable 80: TMU.TCR[2]D R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System