SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA84 Register descriptionsDMAC.CTRL[n] where n is in the range [3:0] 0x000028 + (n * 0x28)Field Bits Size Volatile? Synopsis TypeDESTINATION_INCREMENTRESOURCE_SELECT[6:5] 2 — Increment mode of destinationaddressOperationWhen readWhen writtenHARD resetD R A FTRW0: Destination address incremented (by transfer.sizebytes)1: Destination address decremented (by transfer.sizebytes)2: Destination address is neither incremented ordecremented. All DMA channel n stores will be to thesame address.3: Field is reserved.Returns current valueUpdates current valueUndefined[10:7] 4 — Selects transfer request source RWOperationWhen readWhen writtenHARD reset 00: Auto request1: Peripheral 0 transfer request2: Peripheral 1 transfer request3: Peripheral 2 transfer request4: Peripheral 3 transfer request5: TMU transfer request6: SCIF transmit transfer request7: SCIF receive transfer request[15:8]: Values reserved.Returns current valueUpdates current valueTable 26: DMAC.CTRL[n] registerSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0