SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA272 Clock pulse generator (CPG)CPRC.FRQ - Frequency control register0x0000Field Bits Size Volatile? Synopsis TypeRESERVED [31:24] 8 — Reserved RESOperationReservedWhen read Returns 0When writtenHARD reset 0IgnoredTable 105: The FRQ CONTROL registera. PLL2 not implemented in the Eval Chipb. Field CKOEN is not implemented in the Eval Chip.CPRC.PLL - PLL1 control register10x0008Field Bits Size Volatile? Synopsis TypeMDIV [7:0] 8 — Pre-divider RWOperationWhen readWhen writtenHARD resetParameter for programming PLL1Returns current valueUpdates current valueThis register may only be written when FRQ.PLL1EN is ‘0’.Otherwise any writes are ignored.Only certain values, as defined in the product datasheet, maybe written. All other values are reserved and give undefinedbehavior.D R A FT1 in the Eval chipTable 106: CRP.CPLL control registerSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAClock pulse generator (CPG) 273CPRC.PLL - PLL1 control register10x0008Field Bits Size Volatile? Synopsis TypeNDIV [15:8] 8 — Feedback divider RWOperationWhen readWhen writtenHARD resetParameter for programming PLL1Returns current valueUpdates current valueThis register may only be written when FRQ.PLL1EN is ‘0’.Otherwise any writes are ignored.Only certain values, as defined in the product datasheet, maybe written. All other values are reserved and give undefinedbehavior.32 in the eval chipPDIV [18:16] 3 — Post divider RWOperationWhen readWhen writtenHARD resetParameter for programming PLL1Returns current valueUpdates current valueThis register may only be written when FRQ.PLL1EN is ‘0’.Otherwise any writes are ignored.Only certain values, as defined in the product datasheet, maybe written. All other values are reserved and give undefinedbehavior.0 in the eval ChipTable 106: CRP.CPLL control registerD R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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Page 269 and 270: PRELIMINARY DATAPower down 255Inter
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Page 273 and 274: PRELIMINARY DATAClock, powerand res
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Page 293 and 294: PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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