SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

ivPRELIMINARY DATA2.3 Cache coherency support 192.3.1 Flush 192.3.2 Purge 202.3.3 Coherency maintenance 202.3.4 Use of coherency transactions 212.4 Other features 212.4.1 Module powerdown 212.4.2 Debug features 222.5 SH-5 SuperHyway implementation 222.5.1 Supported transactions 232.5.2 Implementation 232.5.3 Data organization 242.5.4 SH-5 physical memory organization 252.6 SH-5 physical address map 262.6.1 SH-5 debug link 292.7 SH-5 conventions 292.7.1 Memory blocks 292.7.2 Control registers 302.7.3 Version control registers 342.7.4 P-error flags 372.7.5 M-error flags 412.7.6 Memory map conventions 412.7.7 P-module specification standards 422.8 SH-5 endianess and data mapping 432.8.1 Accessing memory 432.8.2 Accessing device registers 432.8.3 Accessing PCI memory space 442.8.4 Using the SHdebug link 442.8.5 SuperHyway byte lane mapping 44D R A FT2.9 SH-5 undefined behavior 472.9.1 SH-5 chip-level architecturally undefined behavior 472.9.2 SH-5 module-level architecturally undefined behavior 482.9.3 Unresponsive modules 50SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0