SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA2 IntroductionEval chip featuresSDRAM interface SDR/DDR32/64-bit, 133 MHz, 64 Mbyte, 256 MbyteSupport four open banksSupport both PC100 and 133 MHz DDRSDRAMSupport power saving idle / standby statesTarget parts: Hitachi P/N: 54S64XXD2 &Intel PC100 SDRAM standardMultiple timers32-bit timer with auto reload, interruptsConfigurable input clocksReal time clockOn-chip oscillator circuitBuilt-in clock, calendar, alarm, IRQInterrupt controllerConfigurable prioritiesInternal peripheral interruptsDebug supportSCIFHigh speed debug interface (100 MHz),independent of JTAGDevelopment host can access entireinternal address space, non-intrusivelyCPU can boot from debug adapterinterfaceCPU core has code address, operand andopcode watchpoints plus branch trace andfast printf functionsWatchpoints and trace on internal bus(SuperHyway)All watchpoints can send trace packets todebug link (non-intrusively) or generateCPU debug trapPerformance counters for CPU core andbus parametersUART FIFO serial interface with DMA16 byte FIFOS/W configured baud clock generatorPower management unitTable 1: FeaturesControl unit and peripheral power savingmodesWatchdog timer fuction (reset hard andsoft)D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAIntroduction 3DM_CLKDM_SYNCDM_REQ_NDM_ACK_NDM_TRIN_NDM_TROUT_NDM_D[3:0]DATA[0:63]BA[1:0]ADDR[12:0]DQMRAS_NCAS_NCLKCLK_NCKECS_NWE_NDS_NAD[31:0]C/BE[3:0]PARPCI_CLKFRAME_NTRDY_NIRDY_NSTOP_NIDSELDEVSEL_NREQ0_NGNT0_NREQ[3:1]_NGNT[3:1]_NLOCKDEBUGEMISDRAM/DDRPCI66 MHzBUSTRACEWatchSuperHywayDebugtracewatchCPUexecutionunitsD R A FTSuperHywayexpansionsocketCache/MMUDMAFlashEMIRTCTMUSCIFINTCClockPowerResetADDR[23:0]DATA[15:0]OE_NWE_NCS[4:0]_NEXTALXTALTCLKSCKRXDTXDCTSRTSIRL[0:3]NMIEXTALCLK_MD[0:2]STATUS[0:1]Figure 1: Eval chip block diagram05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
Page 1 and 2: PRELIMINARY DATASuperH TM (SH)64-Bi
Page 3 and 4: PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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