SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 75The set of supported p-error flags in DMAC.VCR is given in Table 21. The bit positionsin this table are relative to the start of the DMAC.VCR.PERR_FLAGS field; this fieldstarts at bit 0 of DMAC.VCR.Bit name Bit Size Volatile? Synopsis TypeERR_RCV 0 1 ✓ An error response has beenreceivedOperationWhen readWhen writtenHARD reset 0D R A FTRWThis bit is set by the module hardware if an error responseis received by the module port or module from theSuperHyway. It indicates that an earlier request from eitherof these ports was invalid.Returns current valueUpdates current valueERR_SNT 1 1 ✓ An error response has been sent RWOperationWhen readWhen writtenHARD reset 0This bit is set by the DMA hardware if an error response issent by the DMA to the SuperHyway. It indicates that anearlier request to the DMA was invalid.Returns current valueUpdates current valueBAD_ADDR 2 1 ✓ A request for an ‘UNDEFINED’control register has been receivedOperationWhen readWhen writtenHARD reset 0RWThis bit is set by the DMA hardware if the DMA receives arequest for an ‘UNDEFINED’ control register.Returns current valueUpdates current valueTable 21: DMAC.VCR.perr_flags05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System