SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA42 SH-5 conventionsEach 8-byte word that is read will be to the first 8-byte word in a memory block. Ifthe access is to an undefined block then the access will be to an illegal destinationaddress. This will cause the following behavior:• DEBUG.VCR.PERR_FLAGS.BAD_ADDR will be set since the access will cause arequest to an illegal destination to be sent to the DEBUG module.• DEBUG.VCR.PERR_FLAGS.ERR_SNT will be set since the access will cause an errorresponse to be returned by the DEBUG.• If the access is made by a SH-5 CPU, then the VCR of that CPU will haveVCR.PERR_FLAGS.ERR_RCV set since the error response will be received by thatCPU. If the access is made by the host, then the host will be returned an errorresponse over the debug link.• If the access is made by a SH-5 CPU, then the value loaded by the instructioncausing that access will be undefined.If the access is to a control block then the access will return the value of the VCR forthat control block without setting any error bit nor generating an error response.These different behaviors can be used to distinguish accesses to an undefined blockfrom accesses to a control block. The scanning algorithm detects data blocks throughthe VCR values of control blocks. The scanning algorithm itself makes no accesses tolocations within data blocks.This algorithm can be used to classify each SH-5 memory block between 0x00000000and 0xFF000000 (inclusive) as a control block, a data block or an undefined block.Since each VCR value contains a module identity and module version, it is possiblefor software to check for the presence of particular modules and to handle differentmodule versions appropriately.2.7.7 P-module specification standardsThe specification of each module defines the functionality provided by that module.Each module defines the following:D R A FT• The memory map of each memory block associated with that module. Inparticular, the memory map of each control block associated with that moduleindicates whether each control register in that block has ‘DEFINED’,‘RESERVED’ or ‘UNDEFINED’ behavior.• The interactions of that module with the packet-router. This includes the set oftransactions that can be initiated by that module, and the transactions that canbe serviced by that module. The behavior and signalling of error cases is alsofully described.SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0