SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA248 OperationIn serial transmission, the SCIF operates as described below.1 When data is written into SCIF.SCFTDR2, the SCIF transfers the data fromSCIF.SCFTDR2 to SCIF.SCTSR2 and starts transmitting. Confirm that the TDFE flag inthe serial status register (SCIF.SCFSR2) is set to 1 before writing transmit data toSCIF.SCFTDR2. The number of data bytes that can be written is at least 16(transmit trigger setting).2 When data is transferred from SCIF.SCFTDR2 to SCIF.SCTSR2 and transmission isstarted, consecutive transmit operations are performed until there is notransmit data left in SCIF.SCFTDR2. When the number of transmit data bytes inSCIF.SCFTDR2 falls to or below the transmit trigger number set in the FIFO controlregister (SCIF.SCFCR2), the TDFE flag is set. If the TIE bit in SCIF.SCSCR2 is set to 1 atthis time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. Theserial transmit data is sent from the TxD2 pin in the following order.2.1 Start bit: One 0-bit is output.2.2 Transmit data: 8-bit or 7-bit data is output in LSB-first order.2.3 Parity bit: One parity bit (even or odd parity) is output. (A format in which aparity bit is not output can also be selected.)2.4 Stop bit(s): One or two 1-bits (stop bits) are output.2.5 Mark state: 1 is output continuously until the start bit that starts the nexttransmission is sent.3 The SCIF checks the SCIF.SCFTDR2 transmit data at the timing for sending thestop bit. If data is present, the data is transferred from SCIF.SCFTDR2 to SCIF.SCTSR2,the stop bit is sent, and then serial transmission of the next frame is started. Ifthere is no transmit data, the TEND flag in SCIF.SCFSR2 is set to 1, the stop bit issent, and then the line goes to the mark state in which 1 is output.Figure 33 shows an example of the operation for transmission in asynchronousmode.D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0