SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAFunctionality 955.2.2 Address mapThe memory map of the peripheral bridge is organized as follows:Subsystem Description Address range aBridge state B0 - peripheral bridge status 0x0000000 to 0x000FFFFFExternal S1 to S15: reserved for peripherals 0x0100000 to 0x0FFFFFFINTC P0: interrupt control 0x1000000 to 0x100FFFFCPRC P1: clock power reset controller 0x1010000 to 0x101FFFFTMU P2: timer management unit 0x1020000 to 0x102FFFFSCIF P3: serial control interface with fifo 0x1030000 to 0x103FFFFRTC P4: real time clock 0x1040000 to 0x104FFFFExternal 5-15 P5 to P15: reserved PP-Bus areas 0x1050000 to 0x10FFFFFExternal P16: 15 Mbyte external area 0x1100000 to 0x1FFFFFFTable 30: Peripheral bridge memory mapa. The address is given as an offset from the peripheral bridge base address asdefined in the system organization.Detailed descriptions of each peripheral are described in the associated chapter.D R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System