SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA302 Power management unit (PMU)10.4.6 Sleep modeTransition to sleep modeIf a sleep instruction 1 is executed when STBCR.STBY is cleared to 0, the chip switchesfrom the program execution state to sleep mode. After execution of the sleepinstruction, the CPU halts but its register contents are retained. The on-chipperipheral modules continue to operate, and the clock continues to be output fromthe CLKOUT 2 pin.In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-levelsignal at the STATUS0 pin.Exit from sleep modeSleep mode is exited by means of an interrupt (NMI 3 , IRL, or on-chip peripheralmodule) or a reset. When leaving sleep mode by means of an interrupt (other thanNMI) an interrupt handler is launched if the interrupt is not blocked and notmasked. If the interrupt is blocked or is masked, then the handler is not launchedand execution continues with the next instruction after the sleep instruction.Exit by interruptAn asserted interrupt causes the CPU to exit sleep mode regardless of whether thatinterrupt causes the CPU to handle the exception. The requirements for exceptionhandling to start (that is, launch an interrupt handler) are the same as when theCPU is executing normally. This means that the SR.BL bit is tested and the SR.IMASKis compared to the interrupt’s priority in order to determine if exception handlingshould commence or execution should continue with the instruction following thesleep instruction. Software will typically arrange for SR.BL to be cleared or forSR.IMASK to be reduced, as appropriate, in order for the wake-up interrupt to beaccepted.Exit by resetSleep mode is exited by means of a power- on or manual reset via the NOT_RESETP orNOT_RESETM pins, or a power-on or manual reset executed when the watchdog timeroverflows.D R A FT1. Refer to the CPU architecture manual for constraints on the use of the sleepinstruction.2. CLKOUT not implemented in the Eval Chip3. System will always wake up regardless of IMASK and BL.SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0