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SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA1<strong>64</strong> Register descriptionsRTC.RCR20x3CField <strong>Bit</strong>s Size Volatile? Synopsis TypeADJ 2 1 ✓ Second adjustment RWOperationWhen readWhen writtenHARD reset 0Used for 30-second adjustment. When 1 is written to this bit,a value up to 29 seconds is rounded down to 00 seconds,and a value of 30 seconds or more is rounded up to 1 minute.The frequency divider circuits (RTC prescaler andRTC.R<strong>64</strong>CNT) are also reset at this time. This bit alwaysreturns 0 if readReturns current value0: Normal clock operation (Initial value)1: 30-second adjustment performedRTCEN 3 1 ✓ Oscillator enable RWOperationWhen readWhen writtenHARD reset 1Controls the operation of the RTC’s crystal oscillatorReturns current value0: NRTC crystal oscillator is halted1: RTC crystal oscillator is operated (Initial value)Table 71: RTC.RCR2D R A FT<strong>SuperH</strong>, Inc.<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 1: <strong>System</strong> 05-SA-10001 v1.0

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