SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATACache coherency support 55For accesses to addresses on pages which have the PTEL.CB attribute of “device” onlyLoad8/Store8 transactions are used.The most common mode of use of the cache would see the Load32 and Store32transactions most frequently used for cache refills and writebacks.3.3 Cache coherency supportCache coherency transactions are provided primarily to support the integration ofthe PCI bridge into the system. However the coherency support is general and canbe used by any module attached to the system interconnect.3.3.1 Operand cache snoopingIn order to support coherency of access for memory shared between the operandcache and another memory user (for example, a PCI bridge), the CPU allows thecontents of the operand cache to be flushed or purged by external requestors on thesystem interconnect.The semantics of the cache snooping transactions are described below.flushpurge3.3.2 FlushFollowing the completion of a flush transaction to a physicaladdress, the value in the CPU operand cache and the value at thephysical address (as accessed by other memory users) is thesame. The execution of a flush transaction may involve theoperand cache issuing a Store32 transaction to the physicaladdress.Following the completion of a purge transaction to a physicaladdress, the CPU operand cache no longer holds a copy of data atthat address. This execution of a purge instruction may involvethe operand cache issuing a Store32 transaction to the physicaladdress.D R A FTThe two cache control operations flush and purge are described more fully below.The flush transaction has a single operand which is the physical address which is tobe flushed from the cache:flush 05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System