SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA308 Power management unit (PMU)The meaning of the clock units is as follows:Bcyc: SuperHyway clock cyclePcyc: PP-bus clock cycleResetIn the figures in this section, NOT_RESET refers to either NOT_RESETP or NOT_RESETMdepending on the figure title.Power-on resetCKIOSCK2STATUSPLL stabilizationtimeNormal Reset Normal0–5 Bcyc0–30 BcycFigure 45: STATUS output in power-on resetD R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAPower management unit (PMU) 309Manual resetCKIOIn exit from standby modeStandby-interrupt*SCK2STATUS Normal Reset Normal≥ 0 Bcyc0–30 BcycNote: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waitinguntil the end of the currently executing bus cycle.CKIOFigure 46: STATUS output in manual resetOscillation stops Interrupt request WDT overflowWDT countSTATUS Normal Standby NormalD R A FTFigure 47: STATUS output in standby interrupt sequence05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 undefined beha
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
Page 271 and 272: PRELIMINARY DATAUsage notes 257Send
Page 273 and 274: PRELIMINARY DATAClock, powerand res
Page 275 and 276: PRELIMINARY DATAClock pulse generat
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Page 295 and 296: PRELIMINARY DATAWatchdog timer 281C
Page 297 and 298: PRELIMINARY DATAWatchdog timer 283C
Page 299 and 300: PRELIMINARY DATAWatchdog timer 285N
Page 301 and 302: PRELIMINARY DATAPower management un
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Page 327 and 328: PRELIMINARY DATADebug and power man
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Page 331 and 332: PRELIMINARY DATAReset controller 31
Page 337 and 338: PRELIMINARY DATAIndexAAddress 1-2,
Page 339 and 340: PRELIMINARY DATA325Endian 43, 58Bi-
Page 341 and 342: PRELIMINARY DATA327Physical memory
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