SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA284 Watchdog timerCPRC.WTCSR0x0018Field Bits Size Volatile? Synopsis TypeWT/IT 6 1 — Timer mode select RWOperationWhen readWhen writtenHARD reset 0Specifies whether the WDDT is used as a watchdog timer orinterval timer.Returns current value0: Interval timer mode1: Watchdog timer modeThe up-count may not be performed correctly if WT/IT ismodified while the WDT is runningThis field is write restricted. See the final field of this register.TME 7 1 — Timer enable RWOperationWhen readWhen writtenHARD reset 0Specifies starting and stopping of timer operation.Returns current value0: Up-count stopped, WTCNT value retained1: Up-count enabledThis field is write restricted. See the final field of this register.— [31:8] 24 — Reserved RESOperationWhen read Returns 0When writtenHARD reset 0To write to the CPRC.WTCSR register, use a 4-byte -size accesswith these upper bytes set to 0xA50000.D R A FTThis field must be 0xA50000 or the write to all fields isignored.Table 109: CPRC.WTCSRSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0