SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAClock pulse generator (CPG) 26310.2.1 CPG pin configurationTable 100 shows the CPG pins and their functions.Pin name Abbreviation I/O FunctionMode control pins MODE0 Input Set clock operating mode at power onresetMODE1Crystal I/O pins(clock input pins)Clock output pinMODE2XTAL Output Connects crystal resonatorEXTAL Input Connects crystal resonator, or used asexternal clock input pinMODE8 Input Selects use/non-use of crystal resonatorWhen MODE8 = 0, external clock is inputfrom EXTALWhen MODE8 = 1, crystal resonator isconnected directly to EXTAL and XTALBWSEL input Selects the PLL bandwidth according tocrystal resonator frequencyCLKOUT aOutputBWSEL = 0 for a low frequency crystalBWSEL = 1 for a high frequency crystalUsed as external clock output pinLevel can also be fixedClock valid pin CLKVLD a Output 0 when CLKOUT output clock is unstableTable 100: CPG pinsa. Pins CLKOUT and CLKVLD not implemented in the Eval Chip.D R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System