SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

viiiPRELIMINARY DATA7.2.14 Month alarm register (RTC.RMONAR) 1587.2.15 RTC control register 1 (RTC.RCR1) 1607.2.16 RTC control register 2 (RTC.RCR2) 1637.3 Operation 1667.3.1 Time setting procedures 1667.3.2 Time reading procedures 1677.3.3 Alarm function 1687.4 Interrupts 1697.5 Usage notes 1697.5.1 Register initialization 1697.5.2 Crystal oscillator circuit 1698 Timer unit (TMU) 1718.1 Overview 1718.1.1 Features 1718.1.2 Block diagram 1728.1.3 Pin configuration 1738.1.4 Register configuration 1738.2 Register descriptions 1758.2.1 Timer output control register (TMU.TOCR) 1758.2.2 Timer start register (TMU.TSTR) 1768.2.3 Timer constant registers (TMU.TCOR) 1788.2.4 Timer Counters (TMU.TCNT) 1788.2.5 Timer control registers (TMU.TCR) 1798.2.6 Input capture register (TMU.TCPR2) 185D R A FT8.3 Operation 1868.3.1 Counter operation 1868.3.2 Input capture function 1898.4 Interrupts 191SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0