SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAClock pulse generator (CPG) 275CPRC.PLL - PLL1 control register10x0008Field Bits Size Volatile? Synopsis TypePOWER 31 1 ✓ PLL1 power control RWOperationWhen readWhen writtenHARD reset10.2.6 Configuring PLL1Configuring the programmable PLL1 is achieved using the CPRC. PLL controlregister. The frequency of PLL1 output (in Hz) may be calculated from the equationbelow:The parameters in this expression are:Specifies the power state of PLL1Returns current valueD R A FT• FRQ_IN is the frequency in Hz of the SH-5’s input clock• MDIV is the pre-divider defined by PLL.MDIV• NDIV is the feedback divider defined by PLL.NDIV0: PLL1 is off and consuming no power.1: PLL1 is onThis field may only be cleared to ‘0’when FRQ.PLL1EN is ‘0’.Otherwise any writes are ignored.Hardware may set this field to ‘1’ when FRQ.PLL1EN is setto ‘1’.Depends on the clock operating mode after reset.Modes 0 to 4: Reset value = 1. Modes 5 - 6: Reset value = 0.Table 106: CRP.CPLL control registera. Field LOCK not implemented in the Eval Chip (it is always set to 1).⎛FRQ_IN× NDIV--------------------------------------- ⎞ 2 PDIV⎝ MDIV ⎠⁄• PDIV is the post-divider defined by PLL.PDIV05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System