SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA254 SCIF interrupt sources and the DMAC9.4 SCIF interrupt sources and the DMACThe SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI)request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt(RXI) request, and break interrupt (BRI) request.Table 99 shows the interrupt sources and their order of priority. The interruptsources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCIF.SCSCR2. Aseparate interrupt request is sent to the interrupt controller for each of theseinterrupt sources.When transmission/reception is carried out using the DMAC, output of interruptrequests to the interrupt controller can be inhibited by clearing the RIE bit inSCIF.SCSCR2 to 0. By setting the REIE bit to 1 while the RIE bit is cleared to 0, it ispossible to output ERI and BRI interrupt requests, but not RXI interrupt requests.When the TDFE flag in the serial status register (SCIF.SCFSR2) is set to 1, atransmit-FIFO-data-empty request is generated separately from the interruptrequest. A transmit-FIFO-data-empty request can activate the DMAC to performdata transfer.When the RDF flag or DR flag in SCIF.SCFSR2 is set to 1, a receive-FIFO-data-fullrequest is generated separately from the interrupt request. Areceive-FIFO-data-full request can activate the DMAC to perform data transfer.When using the DMAC for transmission/reception, set and enable the DMAC beforemaking the SCIF settings. See the specification of the DMA controller module fordetails of the DMAC setting procedure.When the BRK flag in SCIF.SCFSR2 or the ORER flag in the line status register(SCIF.SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interruptindicates that transmit data can be written, and the RXI interrupt indicates thatthere is receive data in SCIF.SCFRDR2.D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAPower down 255InterruptsourceDescriptionDMACactivationPriority onreset releaseERI Interrupt initiated by receive error flag (ER) Not possible HighRXIBRITXISee the chapter Exceptions in the CPU Architecture manual, for priorities and therelationship with nonSCIF interrupts.9.5 Power downInterrupt initiated by receive FIFO data full flag(RDF) or receive data ready flag (DR)Interrupt initiated by break flag (BRK) or overrunerror flag (ORER)Interrupt initiated by transmit FIFO data emptyflag (TDFE)Table 99: SCIF interrupt sourcesPossible ¦Not possiblePossibleThe SCIF module may be put into a power down state either individually or byputting the chip into standby. See Chapter 10: Clock, power and reset controller onpage 259 for details.In order to guarantee safe transition to a power down state software should firstdeactivate the SCIF. This will ensure that the state of the SCIF is architecturallydefined.The SCIF module can be deactivated by clearing the SCIF.SCSCR2.TE and SCIF.SCSCR2.REflags to ‘0’.Following exit from the power down state, software can re-enable the SCIF moduleoperating by restoring the previous state of the SCIF.SCSCR2.TE and SCIF.SCSCR2.REflags.D R A FTØLow05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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