SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA138 Overview7.1.2 Block diagramFigure 14 shows a block diagram of the RTC.RTCCLKPrescaler16.384 kHz32.768 kHzRTC crystaloscillator128 HzCounter unitR64CNTRSECCNT RMINCNT RHRCNTRDAYCNTATIPRICUIInterruptcontrol unitRWKCNTD R A FTFigure 14: Block diagram of RTCRESET, STBY, etcRTC operationcontrol unitRMONCNTRSECAR RMINAR RHRAR RDAYAR RWKAR RMONARTo registersBus interfaceInternal peripheral module busRCR1RCR2RYRCNTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAOverview 1397.1.3 Pin configurationTable 54 shows the RTC pins.Pin name Abbreviation I/O FunctionRTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillatorRTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillatorClock input/clock output TCLK I/O External clock input pin/input capturecontrol input pin/RTC output pin (sharedwith TMU)Dedicated RTC power supply V CC (RTC) - RTC oscillator power supply pin aDedicated RTC GND pin V SS (RTC) - RTC oscillator GND pin a7.1.4 Register configurationTable 54: RTC Pinsa. Power must always be supplied to the RTC power supply pins even when the RTC isnot used. Power should be supplied to all power supply pins when in Standby mode.Table 55 summarizes the RTC registers.The register addresses are offset from RTCBASE. Refer to the system address mapfor the value of RTCBASE.Name Abbreviation RW Power-onresetFreq.dividercounterSecondcounterMinutecounterManualresetInitializationStandbymodeInitialvalueAddressOffsetRTC.R64CNT R Counts Counts Counts Undefined 0x00 8D R A FTRTC.RSECCNT RW Counts Counts Counts Undefined 0x04 8RTC.RMINCNT RW Counts Counts Counts Undefined 0x08 8AccesssizeTable 55: RTC registers05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 undefined beha
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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Page 109 and 110: PRELIMINARY DATAFunctionality 955.2
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Page 185 and 186: PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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